(a) Field of the Invention
The present invention relates to failure detection in a MOS transistor, and more specifically, to a method for automatically detecting an abnormal condition in a subthreshold region of the MOS transistor.
(b) Discussion of the Related Art
Traditionally, local oxidation of silicon (LOCOS), poly buffer LOCOS (PBL) and recessed LOCOS (R-LOCOS) techniques have been used for isolation in semiconductor integrated circuit devices. However, these techniques result in “bird's beak” shaped portions, and require complicated processing steps. Thus, these techniques are not suitable for use in highly integrated devices. Further, the LOCOS isolation results in a large step difference in the surface of active regions in which electronic circuits, including metal-oxide-semiconductor (MOS) transistors, are to be formed. Thus, a subsequent planarization process is required to alleviate the step difference.
Shallow trench isolation (STI) technology is considered a more viable isolation technique than the LOCOS, because STI does not create bird's beaks shaped portion. Thus, the STI technology results in reduced conversion differences, and occupies less area.
As shown in FIG. 1, the conventional STI fabrication techniques include forming a pad oxide on a semiconductor substrate 10, forming a pad nitride on the pad oxide, and forming a pattern layer for opening an isolation region in the substrate surface. The opened region from the pad oxide and pad nitride is anisotropically etching to form a trench 6 in the semiconductor substrate. A thermal oxide liner is formed in the trench, and the trench is filled with an insulating material, such as silicon oxide 12. During subsequent processing, the pad oxide and pad nitride layers are removed, and active regions are provided in which source and drain regions (S and D), a gate oxide layer 14, a gate electrode layer 16 and a silicide layer 18 are formed. The formation of the active regions typically involves masking, ion implantation, and cleaning steps. The cleaning steps may include cleaning before deposition of sacrificial oxide layer, and cleaning before ion implantation for well formation and threshold voltage. Since the corners of the STI define the boundaries between active and field regions, they are affected by these cleaning steps and a wet etching step for forming the sacrificial oxide layer, which typically use sulfuric acid and hydrofluoric acid solutions that may isotropically remove the top corners of STI leaving a void or “divot” 13 in the oxide fill 12, as shown in FIG. 1.
When a wet etching process is used for forming the gate oxide 14 and three or four wet etching steps are used for the formation of the active regions, the depth of the divot 13 increases. As a result, the junction depths of source and drain regions near to the divot 13 are lower than intended. The presence of divots 13 results in numerous disadvantages. For example, the divots are responsible for a so-called hump or kink phenomenon.
To detect the hump phenomenon, an operator measures the variation of drain current while varying the gate voltage of the MOS transistor to obtain a voltage-current characteristic curve, as shown in FIG. 2. By analyzing the curve, the hump phenomenon can be detected (as indicated by “A” in FIG. 2).
This conventional detection method suffers from numerous disadvantages, such as a lack of an automatic measuring algorithm for use in conventional DC measurement equipment.